(1)Field of the Invention
The present invention relates to an SOI (Silicon On Insulator) semiconductor device, and especially relates to a technology of improving the operating voltage of the SOI semiconductor device.
(2)Related Art
In order to electrically separate the semiconductor elements in a semiconductor integrated circuit, the dielectric isolation is often used. In the dielectric isolation, insulating layers are formed at the bottom and on the side of the semiconductor layer, which is the active layer of the semiconductor device. In this specification, this structure is referred to xe2x80x9cdielectric isolation structurexe2x80x9d.
The SOI semiconductor device with the dielectric isolation structure solves problems facing the conventional semiconductor device using the pn junction isolation, i.e., leakage current via the pn junction and unexpected bipolar effects. The SOI semiconductor device with the dielectric isolation structure is effectively used as the high voltage semiconductor device and the semiconductor device for analog switch.
The conventional SOI semiconductor device is disclosed in Japanese Patent Nos. 2896141 and 2878689.
Each of FIGS. 1 and 2 shows the structure of an n-type high voltage MOS (Metal Oxide Semiconductor) transistor as an example of the conventional SOI semiconductor device. An n-type high voltage MOS transistor 100 in FIG. 1 is manufactured as follows. A silicon dioxide film 102 is formed on a main surface of a semiconductor substrate 101, which is a supporting substrate of the SOI substrate. Then, an nxe2x88x92-type semiconductor layer 103, which is to be the active layer of the SOI substrate, overlies the silicon dioxide film 102. An isolation trench 104 extending to the silicon dioxide film 102 is formed on the nxe2x88x92-type semiconductor layer 103 by etching so as not to be affected by the potentials of the adjacent semiconductor elements. On the side walls of the isolation trench 104, silicon dioxide films 105 are formed. The isolation trench 104 is filled with polysilicon 106. As a result, the nxe2x88x92-type semiconductor layer 103 is electrically isolated from the other semiconductor island. More specifically, the nxe2x88x92-type semiconductor layer 103 is an island dielectrically isolated by the silicon dioxide films 102 and 105.
On the surface of the island nxe2x88x92-type semiconductor layer 103, gate oxide films 107, gate electrodes 108, a p-type semiconductor layer 109, a source electrode 112, n+-type semiconductor layers 110 and 111, and drain electrodes 113 are formed to form the n-type high voltage MOS transistor 100. The p-type semiconductor layer 109 is formed to form a channel region. The n+-type semiconductor layers 110 are connected to the source electrode 112 and surrounded by the p-type semiconductor layer 109. The n+-type semiconductor layers 111 are connected to the drain electrodes 113.
An n-type high voltage MOS transistor 150 in FIG. 2 has almost the same structure as the n-type high voltage MOS transistor 100 in FIG. 1. The n-type high voltage MOS transistor 150 is different from the n-type high voltage MOS transistor 100 in forming an nxe2x88x92-type semiconductor layer 114 between the nxe2x88x92-type semiconductor layer 103 and the silicon dioxide film 102 and forming an n+-type semiconductor layer 115 between the nxe2x88x92-type semiconductor layer 103 and the silicon dioxide film 105 so as to connect to the bottom of the n+-type semiconductor layers 111. Here, the impurity concentration is set as relatively low in the nxe2x88x92-type semiconductor layer 114 and the n+-type semiconductor layer 115. By doing so, a depletion layer is also formed around the nxe2x88x92-type semiconductor layer 114 and the n+-type semiconductor layer 115 in the nxe2x88x92-type semiconductor layer 103 so as to improve the operating.
Generally speaking, a voltage of 0V is applied to a semiconductor substrate 101 in the n-type high voltage MOS transistors 100 and 150 in FIGS. 1 and 2. When the potential of the p-type semiconductor layer 109 is almost the same as the potential of the semiconductor substrate 101, and a large and positive voltage is applied to the n+-type semiconductor layers 111, a pn junction diode consisting of the p-type semiconductor layer 109 and the nxe2x88x92-type semiconductor layer 103 is in a reverse bias state. In this case, a depletion layer extends from the interface between the p-type semiconductor layer 109 and the nxe2x88x92-type semiconductor layer 103. Due to the large and positive voltage applied to the n+-type semiconductor layers 111, the voltage of 0V applied to the semiconductor substrate 101, and the voltage applied to the p-type semiconductor layer 109, the depletion layer evenly extends in the nxe2x88x92-type semiconductor layer 103 to reduce the internal electric field.
As a result, avalanche breakdown hardly occurs in the nxe2x88x92-type semiconductor layer 103. The operating voltage of the n-type high voltage MOS transistor depends on the occurrence of the avalanche breakdown in the nxe2x88x92-type semiconductor layer 103. Accordingly, avalanche breakdown prevention can improve the operating voltage in the reverse bias state.
In the conventional SOI semiconductor device, however, especially, when the potential of the n+-type semiconductor layers 111 that are connected to the drain electrodes 113 is almost the same as the potential of the semiconductor substrate 101 as the supporting substrate of the SOI substrate, a depletion layer is not sufficiently formed in the nxe2x88x92-type semiconductor layer 103. As a result, the operating voltage in the reverse bias state, which mainly depends on the avalanche breakdown, conspicuously deteriorates.
More specifically, in the reverse bias state, in which a large and negative voltage is applied to the p-type semiconductor layer 109, a general voltage of 0V is applied to the semiconductor substrate 101, and a voltage of 0V is applied to the n+-type semiconductor layers 111, the semiconductor substrate 101 and the n+-type semiconductor layers 111 are at the same potential. This adversely affects the extension of the depletion layer. As a result, the depletion layer extending from the pn junction interface of the between the p-type semiconductor layer 109 and the nxe2x88x92-type semiconductor layer 103 does not sufficiently extend to reach regions of the nxe2x88x92-type semiconductor layer 103 under the n+-type semiconductor layers 111. Accordingly, the electric field strength arises in the nxe2x88x92-type semiconductor layer 103 and the avalanche breakdown tends to occur to drastically deteriorate the reverse bias voltage of the n-type MOS transistor.
As has been described, the operating voltage cannot be kept relatively high in any reverse bias state according to the conventional SOI semiconductor device structure. The avalanche breakdown tends to easily occur to deteriorate the operating voltage in a specific condition.
It is accordingly the object of the present invention to provide an SOI semiconductor device with relatively high operating voltage in any reverse bias state.
The above-mentioned object may be achieved by an SOI semiconductor device including: a first semiconductor layer; a second semiconductor layer that is formed on a first part of a first main surface of the first semiconductor layer; a third semiconductor layer with a conductivity type different from a conductivity type of the second semiconductor layer, the third semiconductor layer being formed on a second part of the first main surface of the first semiconductor layer, the second part being separated from the first part; a fourth semiconductor layer with a conductivity type different from a conductivity type of the first semiconductor layer, he fourth semiconductor layer being formed on a second main surface of the first semiconductor layer; and a first insulating layer that is formed on a main surface of the fourth semiconductor layer opposite to the first semiconductor layer, wherein the fourth semiconductor layer includes an impurity of an amount that is large enough so as not to be completely depleted even when a reverse bias voltage is applied between the second and third semiconductor layers.
In the SOI semiconductor device, the fourth semiconductor layer is not completely depleted when a reverse bias voltage is applied between the second and third semiconductor layers. As a result, the fourth semiconductor layer, which is not completely depleted, keeps the potential almost constant at the bottom of the first semiconductor layer and the depletion layer is easy to extend in the first semiconductor layer. Also, by applying a reverse bias voltage to the pn junction comprising the fourth and first semiconductor layers, a depletion layer extends from the pn junction to the first semiconductor layer. Accordingly, when any reverse bias voltage is applied between the second and third semiconductor layers, the depletion layer can be evenly extend in the first semiconductor layer and the internal electric field is reduced, so that an SOI semiconductor device with a favorable operating voltage at the reverse bias state is realized.
Here, it is preferable to set the impurity amount per unit area in the fourth semiconductor layer as larger than 3xc3x971012/cm2 or larger than 1.5 times the impurity amount per unit area in the first semiconductor layer. By doing so, the fourth semiconductor layer can be prevented from being completely depleted. Also, the depletion layer formed at the pn junction comprising of the first and fourth semiconductor layers by a reverse bias extends more widely on the side of the first semiconductor layer to help the depletion layer in the first semiconductor layer evenly extend.
The above-mentioned object may also be achieved by the SOI semiconductor device, wherein an isolation trench is formed in an outer region of the first semiconductor layer so as to surround the second and third semiconductor layers and be deep enough to reach the first insulating layer, and a second insulating layer is formed on an side wall of the isolation trench. As a result, even if other semiconductor elements are formed adjacent to the SOI semiconductor device on the same semiconductor substrate, the SOI semiconductor device is not affected by the potential of the other semiconductor elements and operates with stability. Further, the above-mentioned object may also be achieved by the SOI semiconductor device, wherein a fifth semiconductor layer with the same conductivity type as the conductivity type of the fourth semiconductor layer is formed at an interface between the first semiconductor layer and the second insulating layer. As a result, pn junction separation is realized by the first and fifth semiconductor layers, and the effects of the potential of the adjacent semiconductor elements are further reduced.
In addition, when the isolation trench is filled with an electrically conductive material, the electrically conductive material is provided with an electrode. When an voltage of the same potential as the voltage applied to the insulating layer is applied to the electrode, the SOI semiconductor device is electrically shielded. As a result, the effects of the potential of the adjacent semiconductor elements are further reduced.